High Speed Shared Memory Networks in Hardware in the Loop Applications
As aircraft avionics systems become more and more integrated and complex, the overall costs and duration of system verification and validation efforts continue to increase and contribute to the rising costs of new system design. In order to control costs, reduce schedules, and improve overall quality, Distributed Hardware-in-the-Loop (HIL) simulations are increasingly being used to verify integrated modular avionics systems. As these systems become increasingly complex, the distributed system must interface with an ever increasing number of aircraft interfaces, sensors, and actuators which often drives the requirement for a distributed, real-time processing architecture for the HIL system.
This paper provides a brief technical overview of distributed HIL test systems and also explores the use of a high speed Shared Memory Network for data sharing and time synchronization between real time processors in a distributed HIL test system.